| |
Contents
Current
status
Current status and innovation proposals
Joint
proposal for the CA Core
New Teaching
Tools
Current
status
The
following Computer Architecture courses are delivered at FEEN:
- Computer
Systems (semester IV - 3+2+1)
- Computer
Organization (semester V - 2+2+0,VI - 2+2+1)
- Microcomputer Systems and Input/Output Devices
(semester VII - 2+2+1, VIII - 2+2+1)
- Parallel Computer Systems (semester VII - 2+2+0, VIII - 2+2+1)
- Algorithms and Architectures of Specialized Computer Systems
(semester IX - 2+2+1)
Current
status and innovation proposals
| Computer
Systems
|
semester
IV - 3+2+1 |
|
| Prerequisites: |
| • |
Data
representation |
| • |
Data
structure |
| • |
Digital
logic circuits |
| • |
Switching
algebra |
| |
|
| |
|
|
| Main
topics: |
| • |
Instruction
set architecture – ISA |
| • |
Addressing
modes |
| • |
Data
path / control unit |
| • |
Assembly
programming |
| • |
DMA
& interrupts |
| • |
I/O
handling |
|
| Outcomes
(be familiar with) : |
| • |
Instruction
set architecture – ISA |
| • |
Simple
processor organization |
| • |
Assembly
programming |
| |
|
| |
|
| |
|
|
|
| Innovation
proposal: |
| • |
Visualization
of addressing modes |
| • |
Simple
processor: Visualization of instruction execution |
| • |
creation
of testbench programs |
| • |
simulation
of operation |
| • |
Visualization
of interrupt handling and DMA |
|
|
| |
| Computer
Organization
|
semester
V-2+2+0, VI-2+2+1 |
|
| Prerequisites: |
| • |
Processor
organization |
| • |
Assembly
programming |
| • |
Computer
organization |
|
| Main
topics: |
| • |
RISC
and CISC concepts |
| • |
Pipeline
organization |
| • |
Memory
organization |
| • |
Cache
coherency |
| • |
Microprogramming |
|
| Outcomes
(be familiar with) : |
| • |
Scalar
processor architecture |
| • |
Memory
hierarchy |
| • |
Microprogramming |
|
|
| Innovation
proposal: |
| • |
Non-blocking
cache memories |
| • |
RAMBUS
DRAM, SDR and DDR SDRAM |
| • |
RAID |
| • |
Universal
Serial Bus - USB |
|
|
| |
|
| Microcomputer
Systems and I/O devices |
semester
VII-2+2+1, VIII-2+2+1 |
|
| Prerequisites: |
| • |
RISC,
CISC concepts |
| • |
Digital
logic design |
| • |
Assembly
programming |
|
| Main
topics: |
| • |
Microcomputer
System Architecture |
| • |
Microprocessor
Architecture |
| • |
Microcontrollers |
| • |
Programmable
peripheral devices
(parallel and serial data transfer) |
| • |
I/O
devices |
|
| Outcomes
(be familiar with) : |
| • |
Design
of microcomputer/microcontroller systems |
| • |
Organization
of peripheral controllers |
| • |
I/O
devices |
|
|
| Innovation
proposal: |
| • |
New
generation microcontrollers |
| • |
Simulation
of program execution |
| • |
Visualization
of peripheral devices connection (display, keyboard,
interrupt controller, etc) |
|
|
| |
| Parallel
Computer Systems
|
semester
VI-2+2+0, VIII-2+2+1 |
|
| Prerequisites: |
| • |
RISC
and CISC architectures |
| • |
Memory
organization |
| • |
Pipelining
technique, HLL (High Level Language) |
|
| Main
topics: |
| • |
Taxonomy |
| • |
Performances
of parallel systems |
| • |
Advanced
pipelining techniques |
| • |
Processor
arrays, Interconnection networks |
| • |
Multiprocessors
and multicomputers |
| • |
Cache
coherency in multiprocessor systems |
| • |
Interprocessor
communication and synchronization |
| • |
Parallel
programming |
|
| Outcomes
(be familiar with) : |
| • |
Superscalar
processors |
| • |
Super pipeline processors |
| • |
VLIW machines |
| • |
Parallel
processors |
| • |
Cache coherency |
| • |
Parallel programming |
|
|
| Innovation
proposal: |
| • |
Cluster
computing |
| • |
CORBA
programming |
| • |
Concurrent programming with Java Threads |
|
|
| |
| Algorithms
and Architectures of Specialized Computer Systems
|
semester
IX-2+2+1} |
|
| Prerequisites: |
| • |
Graph
theory, CFG, DFG
|
| • |
Digital
signal processing
|
| • |
Digital
logic design HDL (VHDL) |
|
| Main
topics: |
| • |
Mapping
Algorithm onto the Architecture |
| • |
Hardware synthesis |
| • |
Hardware description |
| • |
Special purpose data paths |
| • |
DSP
applications |
|
| Outcomes
(be familiar with) : |
| • |
Hardware
synthesis |
| • |
ASIC, ASIP |
| • |
Simulation, testing and verification |
|
|
| Innovation
proposal: |
| |
Since this is a new
course, there are no innovation proposals |
|
|
| |
| Microprocessor
systems
(Dept. of Electronic) |
semester
VII-2+2+1, VIII-2+2+1 |
|
| Prerequisites: |
| • |
Digital
logic design |
| • |
Programming technique |
|
| Main
topics: |
| • |
Performance
evaluation of computer systems |
| • |
Hardware
structure of simple and complex processors |
| • |
Memory
subsystem, I/O subsystem, I/O technique |
| • |
Pipeline
technique |
| • |
RISC,
CISC and DSP architectures |
| • |
Programming techniques (Assembler, C) |
| • |
Advanced
microprocessor architectures |
|
| Outcomes
(be familiar with) : |
| • |
Design
of microprocessor systems |
| • |
Programming microprocessor systems |
| • |
Integration
of hardware and software |
|
|
| Innovation
proposal: |
| • |
Synthesis
of microprocessor system's constituents using HDL
(VHDL, Verilog, System C) |
| • |
Concepts
of VLIW machines |
| • |
Instruction
level parallelism |
| • |
Speculative execution |
|
|
| |
Embedded
Computing Systems
(new course proposal ) |
|
|
| Prerequisites: |
| • |
Microprocessor
and microcontroller systems |
| • |
RISC and CISC concepts |
| • |
Hardware synthesis (mixed
logic – analog & digital) |
|
| Main
topics: |
| • |
Embedded
Computing |
| • |
Processor
for embedding system |
| • |
Embedded
computing platform |
| • |
Program
design and analysis |
| • |
Hardware
accelerators |
| • |
Networks |
| • |
System
design technique |
|
| Outcomes
(be familiar with) : |
| • |
Hardware-software
codesign |
| • |
System-on-Chip design - (SoC) |
| • |
Multichip
design |
| • |
Configurable computing |
|
|
| |
|
| |
| |
| |
Joint
proposal for the CA Core of Knowledge
by Mile Stojcev, Ivan Milentijevic, Dimitris Kehagias,
Rolf Drechsler, Marjan Gusev
This is a joint proposal for the Computer Architecture (CA) core
of knowledge for Computer Science (CS) students. The core is composed
of three levels. Core levels provide balanced knowledge of both
hardware and software component of computer system. The core incorporates
almost all new aspects in CA. The creation of the core is based
on the experience of the lecturers from different academic institutions
and represents a joint effort on identifying of main topics in the
field of CA.
| Computer
Architecture Core of Knowledge for Computer Science Studies
(CACoreOfKnowledgeForCSStudiesEN.pdf) |
|
| |
|
Full
text of the proposal |
| |
Avaliable
mirrors: |
| |
|
 |
This
site |
84KB |
Acrobat
pdf document |
Top of the page
New
Teaching Tools
SimArch
Application
area
SimArch
is a teaching tool that supports lectures of computer architectures.
SimArch can be adapted to meet requirements of any computer architecture
course. This is a visualization tool that leads to higher quality
lectures. It enables better lecture understanding - the students
are driven through data flows step-by-step.
Functional
requirements
- Visualization
of custom processor architecture.
-
Hardware descriptions have to be stored in separated files.
-
Capabilities of viewing hardware component details.
-
Visualization of instruction flow through processor components.
-
Detailed information of hardware components status need to be
derived from hardware simulation.
-
Adaptation capabilities that enables involving of new lectures.
-
User-friendly interface.
- Easy
software upgrading.
Non-functional
requirements
- Graphical
elements optimized for presentation using video-beam.
-
Basic package distribution contains files with RISC architectures
that are involved in computer architecture courses at Faculty
of Electronic Engineering, University of Nis.
-
Supported platforms: Microsoft? Win9x, Win2000, WinXP.
| Presentation
of SimArch tool (SimArchV10.ppt) |
|
| |
|
Complete
presentation of production matter and tool features |
| |
Avaliable
mirrors: |
| |
|
|
This
site |
170KB |
Power
Point document |
| |
|
 |
This site |
73KB |
Zip
archive |
Top of the page
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