The book Computer architecture and organization contains viii+316 pages of text in B5 format. It treats subjects from Computer organization course, held in third year of study on the Computer Science Department, Faculty of Electronic Engineering, University of Niš. This course is the second one in the series of computer architecture related courses, including introductory, intermediate and advanced courses, that students are offered to at the Department as obligatory as well as elective courses.

The book is divided into following sections: preface, six chapters, two supplements, references and index. The notions of computer architecture and implementation, requirements for computer design and measures for computer performance evaluation are explained in the first chapter. Second chapter is devoted to processor instruction set architecture. All elements that define this architecture are considered. Alternative solutions with their advantages and disadvantages are discussed. The MIPS32 architecture is explained as an informative representative of contemporary RISC architectures. General processor implementation concepts are explained in third chapter of the book. Design techniques for data path and control units are explained through examples of a single cycle as well as a multicycle hypothetical processor synthesis. This is a logical introduction to pipeline processor implementation, which is explained in fourth chapter in the book. Concepts of pipeline processor organization, hazards which appear in these processors and solutions for decreasing negative effects of hazards are treated. The problems related to introduction of multicycle functional units in processor pipeline and ensuring precise exceptions are treated also in this chapter. These subjects are basics for further studies of instruction level parallelism in the following courses on computer architectures.

In the fifth chapter basic elements of computer arithmetics are explained. Basic data operations in integer and floating point formats are comprised. Sixth chapter is devoted to the hierarchically organized computer memory systems. The organizational as well as functional aspects of cache memories, main memories and virtual memories are explained in details. Timing of memory elements generally and timing of pipeline systems are shortly reviewed in two supplements.

Every chapter contains a number of examples accompanied with corresponding solutions, which alleviate understanding of explained concepts. Explanation is clear and synoptic, based on contemporary concepts of computer architectures and implementation.